EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...